1. Field of the Invention
This invention relates generally to a digital scan converter suitable for use with a high definition television receiver in which the number of horizontal lines of a video signal is doubled to thereby display a picture of high definition.
2. Description of the Prior Art
In a digital scan converter, a standard composite color video signal is supplied to a luminance/chrominance (Y/C) signal processor circuit which generates standard red, green and blue analog primary color signals R,G and B. The red, green and blue analog primary color signals are supplied to an (analog-to-digital) A/D converter and thereby converted to red, green and blue digital primary color signals which are written in a memory at one speed and read therefrom at a faster speed for achieving the scan conversion by which the number of the horizontal scanning lines is doubled. The scan-converted red, green and blue digital primary color signals read from the memory are supplied to (digital-to-analog) D/A converter in which they are converted to scan-converted red, green and blue analog primary color signals. The input standard composite color video signal is also supplied to a deflection integrated circuit (IC) which generates a composite synchronizing signal and a composite blanking signal. Conventionally, the composite blanking signal is provided by an automatic frequency control (AFC) circuit incorporated in the deflection IC and is applied to the Y/C processor circuit for carrying out the blanking of the red, green and blue primary color signals generated by the Y/C processor circuit. Problems arise if the foregoing conventional arrangement for blanking the three primary color signals is employed in a digital scan converter in which a horizontal synchronizing pulse from the deflection IC is supplied to a second AFC circuit and a voltage controlled oscillator (VCO) is controlled by the output signal from the second AFC circuit to provide a clock signal supplied to a writing address counter and a reading address counter, with the address signals therefrom being supplied through a selector to the memory for controlling the writing and reading of the latter, and with the address signal from the reading address counter being further supplied to a synchronizing signal generator circuit which generates a horizontal synchronizing pulse synchronized with the reading address counter and supplied to the second AFC circuit. Thus, the input video signal and the address signal are synchronized with each other. However, the AFC circuit incorporated in the deflection IC for providing the composite blanking signal and the second AFC for controlling the VCO are not synchronized with each other. As a result of the foregoing, jitter components of the two AFC circuits may appear to be multiplied with each other. In that case, the blanking periods of the red, green and blue primary color signals will overlap the writing address periods of the memory so that the blanking period will appear as a black area at the left end or right end of the displayed picture.